The present invention relates to a clocked logic gate circuit in which speedup and facility are realized.
For a prior example of a logic gate circuit, a clocked cascade voltage switch logic circuit (CVSL) (hereinafter called clocked CVSL) is known which is described at pages 144 and 145 of "Principle of CMOS VLSI Design: A Systems Perspective" supervised and translated by Tomisawa and Matsuyama and published by Maruzen Co., Ltd. (1988), which is translation of the original publication of the same title by Neil H. E. Weste & Karman Eshraghian. FIG. 3 shows the above circuit.
The above clocked CVSL is the same as two domino gates operated by true inputs and their complementary inputs with a minimized logic tree. This type logic is superior to a domino logic in that merely a logic with an arbitrary logical expression can be generated and a complete logic family can be constituted. The above logic is superior to a complementary metal-oxide semiconductor (CMOS) logic circuit and a path transistor logic circuit in terms of high speed.